1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor memory device and more particularly to a manufacturing method of a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as a DRAM).
2. Description of the Related Art
Advancement of high integration of DRAM has facilitated micronization of memory cells using DRAM. Difficulties with micronizing the memory cells include providing sufficient memory capacitance in spite of the fact that the memory cells are micronized while forming cell transistors having desirable characteristics. Stacked type capacitors having a charge storage portion stacked on the cell transistor have been adopted as a means for providing sufficient cell capacitance. On the other hand, as for the characteristics of the cell transistors, controlling diffusion layer concentration is a factor to be considered in connection with the micronization of the memory cells. When considering shortening a channel length, the presence of thermal treatment processes such as flattening of an interlayer insulating film and formation of a capacitance portion makes it so that the expansion of a diffusion layer depth cannot be controlled so that a short channel effect of transistors is made more noticeable. Thus, such transistors may be difficult or impossible to use as cell transistors.
A proposed solution to such problems is the use of so called trench gate type transistors, which have a gate electrode buried in a trench (groove) previously formed in a semiconductor substrate. This trench gate type transistor reduces the short channel effect by lengthening the effective channel length by means of the formation of the gate electrode in the trench. However, the long channel length generally increases channel resistance and thus decreases drivability of the transistor. As the drivability of the transistor decreases, the transistor becomes less suitable for performing high speed operation as a semiconductor device. However, it is not as critical to micronize driving circuits and signal processing circuits arranged around the memory cells in which it is desirable to perform a high speed operation as it is to micronize the cell transistors themselves. For this reason, it is preferable to use conventional planer type transistors in the interest of high speed operation over micronization. However, combining the planer type transistors for the drive and signal processing circuits with trench type transistors for the memory cells creates a problem in that individual formations of the two type transistors, each having different structures, in the single semiconductor device results in an increase in manufacturing steps.
A method of forming the two type transistors in a single semiconductor device without too much of an increase in the manufacturing steps is disclosed in Laid Open Japanese Patent Application No. Heisei 7-66297. FIGS. 1A, 1B, and 1C shows a structure of a DRAM like that disclosed in this patent application. FIGS. 1A and 1B show a memory cell section, and FIG. 1C shows a sectional view of the structure of a periphery circuit section. The DRAM has a gate electrode which is formed using an electrode layer serving as a bit line in the memory cell array. The formation method of the DRAM will be described briefly. As shown in FIG. 1A, a trench 2 is formed in a silicon substrate 1 and a gate electrode 4 is buried in the trench 2 interposed by a gate insulating film 3, whereby a transistor in a memory cell is formed. Thereafter, as shown in FIGS. 1B and 1C, a bit line 7 in the memory cell with a polycide structure is formed, which is formed of a polycrystalline silicon film 6 and a tungsten silicide film 5. On the other hand, as shown in FIG. 1B, in the periphery circuit section, a gate electrode 10 of the transistor is formed using the same layers 8 and 9 as the polycrystalline silicon film 6 and the tungsten silicide film 5 constituting the bit line 7 in the memory cell.
In the foregoing conventional semiconductor memory device, the gate electrode of a transistor of the periphery circuit section is formed of the same film constituting the polycide layer, which is formed after the formation of the cell transistor and constitutes the bit line. The transistor of the periphery circuit section will be necessarily formed after the formation of the cell transistor. Therefore, when the gate insulating film (oxide film) of the transistor constituting the periphery circuit section is formed, an interlayer insulating film between the gate electrode and the word/bit line are also formed in the cell transistor side. In such situation, when the gate oxidation is performed for the periphery circuit section, reliability of the gate insulating film of the transistor constituting the periphery circuit section is deteriorated due to influences of impurities and the like, contained in the gate electrode or the interlayer insulating film formed in the memory cell array section.
Furthermore, the bit line located above the cell transistor is used as the gate electrode of the transistor of the periphery circuit section. Specifically, on the formation of the gate electrode of the transistor constituting the periphery circuit section, a high step difference is created by the interlayer insulating film between the gate electrode of the cell transistor and the word/bit line. If this high step difference is present locally, the unetched portion is left in the step difference after etching of the gate electrode of the transistor of the periphery circuit section. As a result, the formation of the gate electrode becomes difficult.
To solve this problem, it is possible to make the inclination of the step difference gentle. For this purpose, the distance between the cell array section and the periphery circuit must be large. This is contrary to the recent trend to reduce the device area. Furthermore, when the bit line is micronized, a focus margin is reduced in photolithography processes, so that flattening of the underground layer is needed. However, in the foregoing semiconductor memory device, the step difference between the bit line of the transistor of the memory cell array section, and the gate electrode of the transistor of the peripheral circuit section is too large, so that patterning for the bit line becomes difficult or impossible.